The present invention relates to a semiconductor device comprising a leadless chip carrier provided with a semiconductor chip thereon. In particular, it relates to an improvement of the structure of a chip carrier having a semiconductor memory chip thereon.
The increasingly larger scale of computer systems has brought along with it a sharp rise in the number of semiconductor elements, for example semiconductor memory elements, used per system. This would normally cause a drop in computing speed, due to the increased wiring length, and larger system external dimensions. As a means to prevent this, large amounts of packaged semiconductor memory elements have begun to be used in recent times.
FIG. 1A is a cross-sectional view of a conventionally packaged semiconductor memory element having leadless chip carrier.
FIG. 1B is a bottom view of FIG. 1A.
Referring to FIG. 1A, a ceramic substrate 1 is provided with a ceramic frame 2 through inner connections 4, of which the surface portion is plated with gold, etc. Outer connections 5, also plated with gold, etc. extend from the inner connections 4 and connect to terminals extending to the bottom surface of the ceramic substrate 1. A cap 8, made of, for example, metal, is connected to the ceramic frame 2 through cap-soldering metallized layer 7 and through a soldering material 9 of, for example, brazed alloy. In the recessed portion of the ceramic substrate 1, a semiconductor device, for example, a semiconductor memory chip 10, is provided through a gold/silicon layer 13 and through a chip stage 3 on which gold is plated. The semiconductor memory chip 10 is electrically connected to the inner connections through bonding pads 11 and through bonding wire 12. Thus, the semiconductor memory chip 10 is protected from mechanical impact and the harmful surrounding atmosphere.
Referring to FIG. 1B, the bottom of the ceramic substrate 1 is provided with a plurality of stripe shaped terminals 6, whose exposed surfaces are plated with gold, for electrical connection with the outer connections 5.
FIG. 2 is schematic cross-sectional view of the conventionally packaged semiconductor memory element shown in FIG. 1A and referred to here by the numeral 14 and a connection substrate 15.
The packaged semiconductor memory element 14 is defined as consisting of a cap 8, a semiconductor memory chip 10, ceramic substrate 1, which is a leadless chip carrier, and chip selecting terminals.
As shown in FIG. 2, the packaged semiconductor memory element 14 is mounted on a connection pattern 16 provided on the connection substrate 15 by soldering the terminals 6 on the bottom of the packaged semiconductor memory element 14 to the connection pattern 16. The soldered portion is illustrated by reference numeral 17 in FIG. 2. Thus, in the conventional structure of the packaged semiconductor memory element, the region wherein the semiconductor memory element contacts the connection substrate 15 is very small since the region is only the portion of the terminals 6 on the bottom of the packaged semiconductor memory element 14.
When the packaged semiconductor memory is working, the semiconductor memory chip 10 usually becomes heated. Some of this heat is conducted to the ceramic substrate 1. A small amount of the heat generated in the semiconductor memory chip 10, therefore, is conducted to the connection substrate 15 through the ceramic substrate 1. Most of the heat generated in the semiconductor memory chip 10, however, remains within the chip, though some heat is emitted from the surface of the semiconductor memory chip 10 to the surrounding atmosphere. Therefore, the semiconductor memory chip 10 is not sufficiently cooled or heat sunk.
The increased temperature of the semiconductor memory chip 10 raises the temperature of the surrounding atmosphere, further reducing the effect of cooling or heat sinking of the semiconductor memory chip 10. This results in an increased temperature of the packaged semiconductor memory element 14 and a reduced function thereof. This in turn makes it necessary to provide space between the semiconductor memory chips to increase the cooling or heat sinking effect, which blocks improvement of the element mounting or package density.